Various stages of semiconductor device manufacturing can often include the deposition of multiple layers of a variety of materials. Such multi-layer manufacturing often includes, repeating for each layer of the device, a step of depositing a conductive or insulating layer on a wafer and a lithography step of coating a resist material as a photosensitive agent on the layer, subjecting the resist material to light exposure with a circuit pattern on a reticle disposed therebetween, developing the pattern and etching the layer with use of the remaining resist material as a mask to form the circuit pattern on the wafer in the layer.
Pattern registration, or pattern alignment, is a key part of successful photolithography. During the manufacture of semiconductor devices and integrated circuits, many masks can be used in succession and in almost all cases, any given mask will need to be aligned relative to its predecessors with a degree of precision that is at least as well controlled as other pattern-related features such as line width so that successive patterns are aligned.
When the circuit pattern of a successive layer is positionally shifted (i.e., does not line up properly) relative to a pattern in an underlying layer, the circuit can become disconnected or short-circuited, which results in the production of a faulty or defective device. Accordingly, to avoid misalignment of successive layers by shifting of their respective patterns during lithography, the lithography exposure apparatus is often designed and equipped to detect alignment marks (i.e., pattern registration marks) provided in the device in an underlying layer, and subsequently position the successive layer pattern on the basis of the location of the alignment marks in the underlying layer.
One existing method of providing layer-upon-layer pattern alignment in multilayer semiconductor devices is through the use of a pattern registration mark format known as “box-in-box.” The box-in-box pattern registration mark design and method consists of etching an outer trench having a box (e.g., square or rectangular) shape into a first layer of a semiconductor device and partially filling the box trench with a conformal material such that the bottom and the side walls of the box trench are covered, depositing a second layer of material on the first layer wherein the outer box is detectable in the upper material layer of the second layer due to the topography of the partially filled outer box in the first layer, and the placement of a subsequent pattern (i.e., a smaller box-shaped mask) for etching the second layer by aligning the smaller box-shaped material, which serves as a mask, on the upper layer relative to the outer box formed in the lower layer.
Unfortunately, such known box-in-box registration methods can be inaccurate as the center of the outer box trench can often be very difficult to correctly measure in practice due to unintended re-positioning of the material partially filling the outer box and/or the added fill of residue from planarization processes. More particularly, during the use of such box-in-box registration processes, after the outer box is formed in the first layer, it is covered along with the upper material layer of the first layer with a conformal material layer. Subsequent to the deposition of this conformal material layer over the first layer and in the outer box, all of the conformal material on the upper material layer of the first layer, other than that which is located in the outer box, is removed prior to deposition of the second layer. Two of the commonly employed methods for removing the conformal material outside of the outer box include dry etching and chemical-mechanical polishing (CMP). Unfortunately, neither method is entirely suitable for accurate pattern registration.
Dry etching can selectively remove the material outside of the outer box, but can also cause damage to the etched surfaces and more importantly can damage the interface between the first layer and second layer. Chemical-mechanical polishing, while not causing interface damage like dry etching, suffers from the difficulty associated with the shift and/or rotation of the position of the material located in the outer trench. As the CMP process is carried out, the material deposited in the outer box can become lopsided due to residue from the CMP process such that one side wall of the trench is more heavily coated than another side. As a result, the center of the trench identified by the material partially filling the outer box trench is detected at a location that does not correspond with the center of the outer box trench. When a subsequent pattern is then aligned based on the outer box, that subsequent pattern is also shifted in an amount roughly equivalent to the error associated with the shift of the outer box.
Accordingly, a need exists for new pattern registration mark designs and methods of aligning patterns in the art of semiconductor manufacturing and photolithography.